729 lines
19 KiB
C
729 lines
19 KiB
C
/*
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* Portions Copyright 2008, 2009 VMware, Inc.
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*/
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#ifndef _X86_64_BITOPS_H
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#define _X86_64_BITOPS_H
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#if defined(__VMKLNX__)
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#include "vmkapi.h"
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#endif /* defined(__VMKLNX__) */
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/*
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* Copyright 1992, Linus Torvalds.
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*/
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#include <asm/alternative.h>
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#define ADDR (*(volatile long *) addr)
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/**
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* set_bit - Atomically set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* This function is atomic and may not be reordered. See __set_bit()
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* if you do not require the atomic guarantees.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*
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* RETURN VALUE:
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* NONE
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*
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*/
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/* _VMKLNX_CODECHECK_: set_bit */
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static __inline__ void set_bit(int nr, volatile void * addr)
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{
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__asm__ __volatile__( LOCK_PREFIX
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"btsl %1,%0"
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:"+m" (ADDR)
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:"dIr" (nr) : "memory");
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}
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/**
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* __set_bit - Set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* Unlike set_bit(), this function is non-atomic and may be reordered.
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* If it's called on the same region of memory simultaneously, the effect
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* may be that only one operation succeeds.
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*/
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static __inline__ void __set_bit(int nr, volatile void * addr)
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{
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__asm__ volatile(
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"btsl %1,%0"
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:"+m" (ADDR)
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:"dIr" (nr) : "memory");
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}
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/**
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* clear_bit - Clears a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* Clears a bit in memory.
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* clear_bit() is atomic and may not be reordered. However, it does
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* not contain a memory barrier, so if it is used for locking purposes,
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* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
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* in order to ensure changes are visible on other processors.
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*
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* RETURN VALUE:
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* None
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*
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*/
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/* _VMKLNX_CODECHECK_: clear_bit */
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static __inline__ void clear_bit(int nr, volatile void * addr)
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{
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__asm__ __volatile__( LOCK_PREFIX
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"btrl %1,%0"
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:"+m" (ADDR)
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:"dIr" (nr));
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}
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static __inline__ void __clear_bit(int nr, volatile void * addr)
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{
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__asm__ __volatile__(
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"btrl %1,%0"
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:"+m" (ADDR)
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:"dIr" (nr));
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}
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#define smp_mb__before_clear_bit() barrier()
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#define smp_mb__after_clear_bit() barrier()
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/**
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* __change_bit - Toggle a bit in memory
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* @nr: the bit to change
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* @addr: the address to start counting from
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*
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* Unlike change_bit(), this function is non-atomic and may be reordered.
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* If it's called on the same region of memory simultaneously, the effect
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* may be that only one operation succeeds.
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*/
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static __inline__ void __change_bit(int nr, volatile void * addr)
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{
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__asm__ __volatile__(
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"btcl %1,%0"
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:"+m" (ADDR)
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:"dIr" (nr));
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}
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/**
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* change_bit - Toggle a bit in memory
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* @nr: Bit to change
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* @addr: Address to start counting from
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*
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* change_bit() is atomic and may not be reordered.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static __inline__ void change_bit(int nr, volatile void * addr)
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{
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__asm__ __volatile__( LOCK_PREFIX
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"btcl %1,%0"
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:"+m" (ADDR)
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:"dIr" (nr));
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}
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/**
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* test_and_set_bit - Set a bit and return its old state
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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* It tests if the bit at position nr in *addr is 0 or not and sets it to 1.
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* Note that the return value need not be 1 (just non-zero) if the bit was 1.
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*
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* RETURN VALUE:
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* 0 if original bit was 0 and NON-ZERO otherwise
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*/
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/* _VMKLNX_CODECHECK_: test_and_set_bit */
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static __inline__ int test_and_set_bit(int nr, volatile void * addr)
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{
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int oldbit;
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__asm__ __volatile__( LOCK_PREFIX
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"btsl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit),"+m" (ADDR)
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:"dIr" (nr) : "memory");
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return oldbit;
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}
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/**
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* __test_and_set_bit - Set a bit and return its old state
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is non-atomic and can be reordered.
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* If two examples of this operation race, one can appear to succeed
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* but actually fail. You must protect multiple accesses with a lock.
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* It tests if the bit at position nr in *addr is 0 or not and sets it to 1.
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* Note that the return value need not be 1 (just non-zero) if the bit was 1.
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*
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* RETURN VALUE:
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* 0 if original bit was 0 and NON-ZERO otherwise
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*
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* SEE ALSO:
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* test_and_set_bit
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*/
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static __inline__ int __test_and_set_bit(int nr, volatile void * addr)
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{
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int oldbit;
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__asm__(
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"btsl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit),"+m" (ADDR)
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:"dIr" (nr));
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return oldbit;
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}
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/**
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* test_and_clear_bit - Clear a bit and return its old state
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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* It tests if the bit at position nr in *addr is 0 or not and sets it to 0.
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* Note that the return value need not be 1 (just non-zero) if the bit was 1.
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*
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* RETURN VALUE:
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* 0 if original bit was 0 and NON-ZERO otherwise
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*/
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/* _VMKLNX_CODECHECK_: test_and_clear_bit */
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static __inline__ int test_and_clear_bit(int nr, volatile void * addr)
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{
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int oldbit;
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__asm__ __volatile__( LOCK_PREFIX
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"btrl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit),"+m" (ADDR)
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:"dIr" (nr) : "memory");
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return oldbit;
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}
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/**
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* __test_and_clear_bit - Clear a bit and return its old state
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation is non-atomic and can be reordered.
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* If two examples of this operation race, one can appear to succeed
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* but actually fail. You must protect multiple accesses with a lock.
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* It tests if the bit at position nr in *addr is 0 or not and sets it to 0.
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* Note that the return value need not be 1 (just non-zero) if the bit was 1.
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*
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* RETURN VALUE:
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* 0 if original bit was 0 and NON-ZERO otherwise
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*
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* SEE ALSO:
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* test_and_clear_bit
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*/
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static __inline__ int __test_and_clear_bit(int nr, volatile void * addr)
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{
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int oldbit;
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__asm__(
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"btrl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit),"+m" (ADDR)
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:"dIr" (nr));
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return oldbit;
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}
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/**
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* __test_and_change_bit - Toggle a bit and return its old state
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* @nr: Bit to toggle
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* @addr: Address to count from
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*
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* This operation is non-atomic and can be reordered.
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* It also implies a memory barrier.
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* It tests if the bit at position nr in *addr is 0 or not and toggles it.
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* Note that the return value need not be 1 (just non-zero) if the bit was 1.
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*
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* RETURN VALUE:
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* 0 if original bit was 0 and NON-ZERO otherwise
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*
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* SEE ALSO:
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* test_and_change_bit
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*/
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static __inline__ int __test_and_change_bit(int nr, volatile void * addr)
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{
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int oldbit;
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__asm__ __volatile__(
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"btcl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit),"+m" (ADDR)
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:"dIr" (nr) : "memory");
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return oldbit;
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}
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/**
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* test_and_change_bit - Toggle a bit and return its old state
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* @nr: Bit to toggle
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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* It tests if the bit at position nr in *addr is 0 or not and toggles it.
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* Note that the return value need not be 1 (just non-zero) if the bit was 1.
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*
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* RETURN VALUE:
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* 0 if original bit was 0 and NON-ZERO otherwise
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*/
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/* _VMKLNX_CODECHECK_: test_and_change_bit */
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static __inline__ int test_and_change_bit(int nr, volatile void * addr)
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{
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int oldbit;
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__asm__ __volatile__( LOCK_PREFIX
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"btcl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit),"+m" (ADDR)
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:"dIr" (nr) : "memory");
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return oldbit;
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}
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/**
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* constant_test_bit - determine whether a bit is set
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* @nr: bit number to test
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* @addr: addr to test
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*
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* Determines the state of the specified bit.
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* This is used when @nr is known to be constant at compile-time.
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* Use test_bit() instead of using this directly.
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*
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* RETURN VALUE:
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* 0 if the bit was 0 and NON-ZERO otherwise
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*/
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/* _VMKLNX_CODECHECK_: constant_test_bit */
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static __inline__ int constant_test_bit(int nr, const volatile void * addr)
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{
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return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
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}
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/**
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* variable_test_bit - determine whether a bit is set
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* @nr: bit number to test
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* @addr: addr to test
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*
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* Determines the state of the specified bit.
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* This is used when @nr is a variable.
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* Use test_bit() instead of using this directly.
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*
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* RETURN VALUE:
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* 0 if the bit was 0 and NON-ZERO otherwise
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*/
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/* _VMKLNX_CODECHECK_: variable_test_bit */
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static __inline__ int variable_test_bit(int nr, volatile const void * addr)
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{
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int oldbit;
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__asm__ __volatile__(
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"btl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit)
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:"m" (ADDR),"dIr" (nr));
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return oldbit;
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}
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/**
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* test_bit - Determine if bit at given position is set
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* @nr: number of bit to be tested
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* @addr: pointer to byte to test
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*
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* It tests if the bit at position nr in *addr is 0 or not.
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* If the bit number is a constant an optimized bit extract is done.
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* Note that the return value need not be 1 (just non-zero) if the bit was 1.
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*
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* SYNOPSIS:
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* #define test_bit(nr,addr)
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*
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* RETURN VALUE:
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* 0 if the bit was 0 and NON-ZERO otherwise
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*/
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/* _VMKLNX_CODECHECK_: test_bit */
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#define test_bit(nr,addr) \
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(__builtin_constant_p(nr) ? \
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constant_test_bit((nr),(addr)) : \
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variable_test_bit((nr),(addr)))
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#undef ADDR
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#if defined(__VMKLNX__)
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/**
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* find_first_zero_bit - find the first zero bit in a memory region
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* @addr: The address to start the search at
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* @size: The maximum bitnumber to search
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*
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* Finds the first zero bit in a specified memory region
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*
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* RETURN VALUE:
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* Returns the bit-number of the first zero bit, not the number of the byte
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* containing a bit.
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* If result is equal to or greater than size means no zero bit is found
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*/
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/* _VMKLNX_CODECHECK_: find_first_zero_bit */
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static __inline__ long
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find_first_zero_bit(const unsigned long * addr, unsigned long size)
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{
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long d0, d1, d2;
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long res;
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/*
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* We must test the size in words, not in bits, because
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* otherwise incoming sizes in the range -63..-1 will not run
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* any scasq instructions, and then the flags used by the je
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* instruction will have whatever random value was in place
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* before. Nobody should call us like that, but
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* find_next_zero_bit() does when offset and size are at the
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* same word and it fails to find a zero itself.
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*/
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size += 63;
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size >>= 6;
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if (!size)
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return 0;
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vmk_CPUEnsureClearDF();
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asm volatile(
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" repe; scasq\n"
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" je 1f\n"
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" xorq -8(%%rdi),%%rax\n"
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" subq $8,%%rdi\n"
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" bsfq %%rax,%%rdx\n"
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"1: subq %[addr],%%rdi\n"
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" shlq $3,%%rdi\n"
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" addq %%rdi,%%rdx"
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:"=d" (res), "=&c" (d0), "=&D" (d1), "=&a" (d2)
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:"0" (0ULL), "1" (size), "2" (addr), "3" (-1ULL),
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[addr] "S" (addr) : "memory");
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/*
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* Any register would do for [addr] above, but GCC tends to
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* prefer rbx over rsi, even though rsi is readily available
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* and doesn't have to be saved.
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*/
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return res;
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}
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/**
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* find_next_zero_bit - find the first zero bit in a memory region
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* @addr: The address to base the search on
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* @offset: The bitnumber to start searching at
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* @size: The maximum size to search
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*
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* Finds the first zero bit in a specified memory region
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*
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* RETURN VALUE:
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* Returns the bit-number of the first zero bit in a memory region after the
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* specified offset
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* If result is equal to or greater than size means no zero bit is found
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*/
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/* _VMKLNX_CODECHECK_: find_next_zero_bit */
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static __inline__ long
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find_next_zero_bit (const unsigned long * addr, long size, long offset)
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{
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const unsigned long * p = addr + (offset >> 6);
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unsigned long set = 0;
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unsigned long res, bit = offset&63;
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if (bit) {
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/*
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* Look for zero in first word
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*/
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asm("bsfq %1,%0\n\t"
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"cmoveq %2,%0"
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: "=r" (set)
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: "r" (~(*p >> bit)), "r"(64L));
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if (set < (64 - bit))
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return set + offset;
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set = 64 - bit;
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p++;
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}
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/*
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* No zero yet, search remaining full words for a zero
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*/
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res = find_first_zero_bit (p, size - 64 * (p - addr));
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return (offset + set + res);
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}
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/**
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* find_first_bit - find the first set bit in a memory region
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* @addr: The address to start the search at
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* @size: The maximum size to search
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*
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* Finds the first set bit in a specified memory region
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*
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* RETURN VALUE:
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* Returns the bit-number of the first set bit, not the number of the byte
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* containing a bit.
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*
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*/
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/* _VMKLNX_CODECHECK_: find_first_bit */
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static __inline__ long find_first_bit(const unsigned long * addr, unsigned long size)
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{
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long d0, d1;
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long res;
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/*
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* We must test the size in words, not in bits, because
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* otherwise incoming sizes in the range -63..-1 will not run
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* any scasq instructions, and then the flags used by the jz
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* instruction will have whatever random value was in place
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* before. Nobody should call us like that, but
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* find_next_bit() does when offset and size are at the same
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* word and it fails to find a one itself.
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*/
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size += 63;
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size >>= 6;
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if (!size)
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return 0;
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vmk_CPUEnsureClearDF();
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asm volatile(
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" repe; scasq\n"
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" jz 1f\n"
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" subq $8,%%rdi\n"
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" bsfq (%%rdi),%%rax\n"
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"1: subq %[addr],%%rdi\n"
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" shlq $3,%%rdi\n"
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" addq %%rdi,%%rax"
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:"=a" (res), "=&c" (d0), "=&D" (d1)
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:"0" (0ULL), "1" (size), "2" (addr),
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[addr] "r" (addr) : "memory");
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return res;
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}
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/**
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* find_next_bit - find the first set bit in a memory region
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* @addr: The address to base the search on
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* @size: The maximum size to search
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* @offset: The bitnumber to start searching at
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*
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* Finds the first set bit in a specified memory region
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*
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* RETURN VALUE:
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* Position of the first set bit in the specified memory, starting from offset.
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* If none is found, the full word, starting from addr, is searched.
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*/
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/* _VMKLNX_CODECHECK_: find_next_bit */
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static __inline__ long find_next_bit(const unsigned long * addr, long size, long offset)
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{
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const unsigned long * p = addr + (offset >> 6);
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unsigned long set = 0, bit = offset & 63, res;
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if (bit) {
|
|
/*
|
|
* Look for nonzero in the first 64 bits:
|
|
*/
|
|
asm("bsfq %1,%0\n\t"
|
|
"cmoveq %2,%0\n\t"
|
|
: "=r" (set)
|
|
: "r" (*p >> bit), "r" (64L));
|
|
if (set < (64 - bit))
|
|
return set + offset;
|
|
set = 64 - bit;
|
|
p++;
|
|
}
|
|
/*
|
|
* No set bit yet, search remaining full words for a bit
|
|
*/
|
|
res = find_first_bit (p, size - 64 * (p - addr));
|
|
return (offset + set + res);
|
|
}
|
|
|
|
|
|
#else /* !defined(__VMKLNX__) */
|
|
extern long find_first_zero_bit(const unsigned long * addr, unsigned long size);
|
|
extern long find_next_zero_bit (const unsigned long * addr, long size, long offset);
|
|
extern long find_first_bit(const unsigned long * addr, unsigned long size);
|
|
extern long find_next_bit(const unsigned long * addr, long size, long offset);
|
|
#endif /* defined(__VMKLNX__) */
|
|
|
|
/**
|
|
* __scanbit - searches unsigned long value for the least significant set bit
|
|
* @val: The unsigned long value to scan for the set bit
|
|
* @max: The value to return if no set bit found
|
|
*
|
|
* Finds the least significant set bit in specified unsigned long value
|
|
*
|
|
* RETURN VALUE:
|
|
* Index of first bit set in val or max when no bit is set
|
|
*/
|
|
/* _VMKLNX_CODECHECK_: __scanbit */
|
|
static inline unsigned long __scanbit(unsigned long val, unsigned long max)
|
|
{
|
|
asm("bsfq %1,%0 ; cmovz %2,%0" : "=&r" (val) : "r" (val), "r" (max));
|
|
return val;
|
|
}
|
|
|
|
#define find_first_bit(addr,size) \
|
|
((__builtin_constant_p(size) && (size) <= BITS_PER_LONG ? \
|
|
(__scanbit(*(unsigned long *)addr,(size))) : \
|
|
find_first_bit(addr,size)))
|
|
|
|
#define find_next_bit(addr,size,off) \
|
|
((__builtin_constant_p(size) && (size) <= BITS_PER_LONG ? \
|
|
((off) + (__scanbit((*(unsigned long *)addr) >> (off),(size)-(off)))) : \
|
|
find_next_bit(addr,size,off)))
|
|
|
|
#define find_first_zero_bit(addr,size) \
|
|
((__builtin_constant_p(size) && (size) <= BITS_PER_LONG ? \
|
|
(__scanbit(~*(unsigned long *)addr,(size))) : \
|
|
find_first_zero_bit(addr,size)))
|
|
|
|
#define find_next_zero_bit(addr,size,off) \
|
|
((__builtin_constant_p(size) && (size) <= BITS_PER_LONG ? \
|
|
((off)+(__scanbit(~(((*(unsigned long *)addr)) >> (off)),(size)-(off)))) : \
|
|
find_next_zero_bit(addr,size,off)))
|
|
|
|
/*
|
|
* Find string of zero bits in a bitmap. -1 when not found.
|
|
*/
|
|
extern unsigned long
|
|
find_next_zero_string(unsigned long *bitmap, long start, long nbits, int len);
|
|
|
|
static inline void set_bit_string(unsigned long *bitmap, unsigned long i,
|
|
int len)
|
|
{
|
|
unsigned long end = i + len;
|
|
while (i < end) {
|
|
__set_bit(i, bitmap);
|
|
i++;
|
|
}
|
|
}
|
|
|
|
static inline void __clear_bit_string(unsigned long *bitmap, unsigned long i,
|
|
int len)
|
|
{
|
|
unsigned long end = i + len;
|
|
while (i < end) {
|
|
__clear_bit(i, bitmap);
|
|
i++;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* ffz - find first zero in word.
|
|
* @word: The word to search
|
|
*
|
|
* Undefined if no zero exists, so code should check against ~0UL first.
|
|
*
|
|
* RETURN VALUE:
|
|
* Position of the first zero in the word
|
|
*/
|
|
/* _VMKLNX_CODECHECK_: ffz */
|
|
static __inline__ unsigned long ffz(unsigned long word)
|
|
{
|
|
__asm__("bsfq %1,%0"
|
|
:"=r" (word)
|
|
:"r" (~word));
|
|
return word;
|
|
}
|
|
|
|
/**
|
|
* __ffs - find first set bit in word
|
|
* @word: The word to search
|
|
*
|
|
* Undefined if no bit is set, so code should check against 0 first.
|
|
*
|
|
* RETURN VALUE:
|
|
* Position of the first set bit in the word
|
|
*/
|
|
/* _VMKLNX_CODECHECK_: __ffs */
|
|
static __inline__ unsigned long __ffs(unsigned long word)
|
|
{
|
|
__asm__("bsfq %1,%0"
|
|
:"=r" (word)
|
|
:"rm" (word));
|
|
return word;
|
|
}
|
|
|
|
/*
|
|
* __fls: find last bit set.
|
|
* @word: The word to search
|
|
*
|
|
* Undefined if no zero exists, so code should check against ~0UL first.
|
|
*/
|
|
static __inline__ unsigned long __fls(unsigned long word)
|
|
{
|
|
__asm__("bsrq %1,%0"
|
|
:"=r" (word)
|
|
:"rm" (word));
|
|
return word;
|
|
}
|
|
|
|
#ifdef __KERNEL__
|
|
|
|
#include <asm-generic/bitops/sched.h>
|
|
|
|
/**
|
|
* ffs - find first bit set
|
|
* @x: the word to search
|
|
*
|
|
* Finds the first bit set in the referenced word
|
|
*
|
|
* RETURN VALUE:
|
|
* Position of the first set bit
|
|
*/
|
|
/* _VMKLNX_CODECHECK_: ffs */
|
|
static __inline__ int ffs(int x)
|
|
{
|
|
int r;
|
|
|
|
__asm__("bsfl %1,%0\n\t"
|
|
"cmovzl %2,%0"
|
|
: "=r" (r) : "rm" (x), "r" (-1));
|
|
return r+1;
|
|
}
|
|
|
|
/**
|
|
* fls64 - find last bit set in 64 bit word
|
|
* @x: the word to search
|
|
*
|
|
* This is defined the same way as fls.
|
|
*/
|
|
static __inline__ int fls64(__u64 x)
|
|
{
|
|
if (x == 0)
|
|
return 0;
|
|
return __fls(x) + 1;
|
|
}
|
|
|
|
/**
|
|
* fls - find last bit set
|
|
* @x: the word to search
|
|
*
|
|
* Finds last bit set in the specified word
|
|
*
|
|
* RETURN VALUE:
|
|
* The last set bit in specified word
|
|
*/
|
|
/* _VMKLNX_CODECHECK_: fls */
|
|
static __inline__ int fls(int x)
|
|
{
|
|
int r;
|
|
|
|
__asm__("bsrl %1,%0\n\t"
|
|
"cmovzl %2,%0"
|
|
: "=&r" (r) : "rm" (x), "rm" (-1));
|
|
return r+1;
|
|
}
|
|
|
|
#include <asm-generic/bitops/hweight.h>
|
|
|
|
#endif /* __KERNEL__ */
|
|
|
|
#ifdef __KERNEL__
|
|
|
|
#include <asm-generic/bitops/ext2-non-atomic.h>
|
|
|
|
#define ext2_set_bit_atomic(lock,nr,addr) \
|
|
test_and_set_bit((nr),(unsigned long*)addr)
|
|
#define ext2_clear_bit_atomic(lock,nr,addr) \
|
|
test_and_clear_bit((nr),(unsigned long*)addr)
|
|
|
|
#include <asm-generic/bitops/minix.h>
|
|
|
|
#endif /* __KERNEL__ */
|
|
|
|
#endif /* _X86_64_BITOPS_H */
|