ESXi-5.5-U1
This commit is contained in:
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parent
91e0d39c98
commit
89a4bb14d0
79 changed files with 21997 additions and 8736 deletions
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@ -251,13 +251,8 @@ typedef struct vmk_EthHdr {
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typedef struct vmk_VLANHdr {
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/** High four bits of the VLAN ID. */
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vmk_uint8 vlanIDHigh:4;
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/** This field has two different interpretations. */
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union {
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/** The MAC addresses are in canonical format. */
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vmk_uint8 canonical:1;
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/** The frame is eligible to be dropped in the presence of congestion. */
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vmk_uint8 dropEligible:1;
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};
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/** The frame is eligible to be dropped in the presence of congestion. */
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vmk_uint8 dropEligible:1;
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/** Priority tag. */
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vmk_uint8 priority:3;
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/** Low eight bits of the VLAN ID. */
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@ -251,13 +251,8 @@ typedef struct vmk_EthHdr {
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typedef struct vmk_VLANHdr {
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/** High four bits of the VLAN ID. */
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vmk_uint8 vlanIDHigh:4;
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/** This field has two different interpretations. */
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union {
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/** The MAC addresses are in canonical format. */
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vmk_uint8 canonical:1;
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/** The frame is eligible to be dropped in the presence of congestion. */
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vmk_uint8 dropEligible:1;
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};
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/** The frame is eligible to be dropped in the presence of congestion. */
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vmk_uint8 dropEligible:1;
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/** Priority tag. */
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vmk_uint8 priority:3;
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/** Low eight bits of the VLAN ID. */
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@ -1,6 +1,6 @@
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#define BUILD_NUMBER "build-1604073"
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#define BUILD_NUMBER_NUMERIC 1604073
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#define BUILD_NUMBER_NUMERIC_STRING "1604073"
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#define PRODUCT_BUILD_NUMBER "product-build-4509"
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#define PRODUCT_BUILD_NUMBER_NUMERIC 4509
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#define PRODUCT_BUILD_NUMBER_NUMERIC_STRING "4509"
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#define BUILD_NUMBER "build-1623387"
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#define BUILD_NUMBER_NUMERIC 1623387
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#define BUILD_NUMBER_NUMERIC_STRING "1623387"
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#define PRODUCT_BUILD_NUMBER "product-build-4950"
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#define PRODUCT_BUILD_NUMBER_NUMERIC 4950
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#define PRODUCT_BUILD_NUMBER_NUMERIC_STRING "4950"
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13
BUILD.txt
13
BUILD.txt
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@ -1,8 +1,13 @@
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The following assumes the files disclosed for this package have been
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copied to the directory "/usr/vmware/src", and any commands that need to
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be executed for the disclosure should be executed from this directory
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on a "centos-5.3-x64" system (see the file "SYSTEMS.txt" for definition
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of this system).
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copied to the directory "/usr/vmware/src":
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rm -rf /usr/vmware/src
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mkdir /usr/vmware/src
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cp * /usr/vmware/src
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And any commands that need to be executed for the disclosure should be
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executed from this directory on a "centos-5.3-x64" system (see the file
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"SYSTEMS.txt" for definition of this system).
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This package should be built on a "centos-5.3-x64" system. Please see the
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"System Configurations" document for a definition of the configuration
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26
machines.cfgx
Normal file
26
machines.cfgx
Normal file
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@ -0,0 +1,26 @@
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<verify>
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<virtual-infrastructure>
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<address>10.111.110.45</address>
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<username>root</username>
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<password>password</password>
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<vm type="build">
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<id>centos-5.3-x64</id>
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<realname>Rush-CentOS-5.3-x64</realname>
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<os>linux</os>
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<username>root</username>
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<password>welcome</password>
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</vm>
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</virtual-infrastructure>
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<virtual-infrastructure>
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<address>10.111.110.98</address>
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<username>root</username>
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<password>welcome</password>
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<vm type="install">
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<id>BDE-Management-Server</id>
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<realname>management-server</realname>
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<os>linux</os>
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<username>root</username>
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<password>vmware</password>
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</vm>
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</virtual-infrastructure>
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</verify>
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26
vmkdrivers-gpl.odpx
Normal file
26
vmkdrivers-gpl.odpx
Normal file
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@ -0,0 +1,26 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<disclosure>
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<name>vmkdrivers</name>
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<version>gpl</version>
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<category>VMWsource</category>
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<build>
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<target>centos-5.3-x64</target>
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<files>
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<file>vmkdrivers-gpl.tgz</file>
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<file>collect-drivers.sh</file>
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<file>update-drivers.sh</file>
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</files>
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<process>
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<execute>tar xzf vmkdrivers-gpl.tgz</execute>
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<execute>sh ./build-vmkdrivers.sh</execute>
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<execute>mv collect-drivers.sh BLD/build/collect-drivers.sh</execute>
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<execute>cd BLD/build</execute>
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<execute>./collect-drivers.sh</execute>
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</process>
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<deliveries>
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<delivery dir="BLD/build">drivers</delivery>
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<delivery>update-drivers.sh</delivery>
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</deliveries>
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<output>centos-5.3-x64</output>
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</build>
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</disclosure>
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@ -1,5 +1,5 @@
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/*
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* Portions Copyright 2008 - 2010 VMware, Inc.
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* Portions Copyright 2008 - 2013 VMware, Inc.
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*/
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/*
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* ahci.c - AHCI SATA support
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@ -54,7 +54,7 @@
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#endif
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#define DRV_NAME "ahci"
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#define DRV_VERSION "3.0-17vmw"
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#define DRV_VERSION "3.0-18vmw"
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#if defined(__VMKLNX__)
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static int ahci_skip_host_reset = 0;
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@ -634,6 +634,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
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{ PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
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{ PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
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{ PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
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{ PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
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{ PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Wellsburg RAID */
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{ PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
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{ PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
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{ PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
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{ PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
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@ -1968,7 +1971,6 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
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if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
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#if defined(__VMKLNX__)
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if ((irq_stat & PORT_IRQ_PHYRDY) && (ap->link.device[0].sdev)) {
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vmklnx_scsi_device_hot_removed(ap->link.device[0].sdev);
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ata_ehi_push_desc(host_ehi, "hotplug handled");
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}
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#endif
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@ -91,7 +91,7 @@
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#include "bnx2_fw2.h"
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#define DRV_MODULE_NAME "bnx2"
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#define DRV_MODULE_VERSION "2.2.3h.v55.2"
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#define DRV_MODULE_VERSION "2.2.3d.v55.2"
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#define DRV_MODULE_RELDATE "Feb 12, 2013"
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#define RUN_AT(x) (jiffies + (x))
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@ -15,7 +15,7 @@
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#ifndef CNIC_REGISTER_H
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#define CNIC_REGISTER_H
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#define CNIC_REGISTER_MODULE_VERSION "1.72.2.v55.1"
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#define CNIC_REGISTER_MODULE_VERSION "1.72.1.v50.1i"
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#define CNIC_REGISTER_MODULE_RELDATE "February 06, 2013"
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extern int cnic_register_adapter(const char * name, void *callback);
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extern void *cnic_register_get_callback(const char * name);
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@ -15,7 +15,7 @@
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#ifndef CNIC_REGISTER_H
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#define CNIC_REGISTER_H
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#define CNIC_REGISTER_MODULE_VERSION "1.72.2.v55.1"
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#define CNIC_REGISTER_MODULE_VERSION "1.72.1.v50.1i"
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#define CNIC_REGISTER_MODULE_RELDATE "February 06, 2013"
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extern int cnic_register_adapter(const char * name, void *callback);
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extern void *cnic_register_get_callback(const char * name);
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@ -997,6 +997,14 @@ static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
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reg |= (1 << 28);
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ew32(TARC(1), reg);
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/*
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* Disable IPv6 extension header parsing because some malformed
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* IPv6 headers can hang the Rx.
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*/
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reg = er32(RFCTL);
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reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
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ew32(RFCTL, reg);
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return;
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}
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@ -1184,6 +1184,16 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
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ew32(CTRL_EXT, reg);
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}
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/*
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* Disable IPv6 extension header parsing because some malformed
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* IPv6 headers can hang the Rx.
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*/
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if (hw->mac.type <= e1000_82573) {
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reg = er32(RFCTL);
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reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
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ew32(RFCTL, reg);
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}
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/* PCI-Ex Control Registers */
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switch (hw->mac.type) {
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@ -2785,6 +2785,21 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
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ew32(STATUS, reg);
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}
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/*
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* work-around descriptor data corruption issue during nfs v2 udp
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* traffic,just disable the nfs filtering capability
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*/
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reg = er32(RFCTL);
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reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
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/*
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* Disable IPv6 extension header parsing because some
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* malformed IPv6 headers can hang the Rx.
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*/
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if (hw->mac.type == e1000_ich8lan)
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reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
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ew32(RFCTL, reg);
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return;
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}
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File diff suppressed because it is too large
Load diff
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@ -1,7 +1,7 @@
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/*******************************************************************************
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Intel(R) Gigabit Ethernet Linux driver
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Copyright(c) 2007-2009 Intel Corporation.
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Copyright(c) 2007-2013 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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@ -28,10 +28,10 @@
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#ifndef _E1000_82575_H_
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#define _E1000_82575_H_
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#define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
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(ID_LED_DEF1_DEF2 << 8) | \
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(ID_LED_DEF1_DEF2 << 4) | \
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(ID_LED_OFF1_ON2))
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#define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
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(ID_LED_DEF1_DEF2 << 8) | \
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(ID_LED_DEF1_DEF2 << 4) | \
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(ID_LED_OFF1_ON2))
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/*
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* Receive Address Register Count
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* Number of high/low register pairs in the RAR. The RAR (Receive Address
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@ -42,149 +42,150 @@
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* For 82576, there are an additional set of RARs that begin at an offset
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* separate from the first set of RARs.
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*/
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#define E1000_RAR_ENTRIES_82575 16
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#define E1000_RAR_ENTRIES_82576 24
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#define E1000_RAR_ENTRIES_82580 24
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#define E1000_SW_SYNCH_MB 0x00000100
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#define E1000_STAT_DEV_RST_SET 0x00100000
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#define E1000_CTRL_DEV_RST 0x20000000
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#define E1000_RAR_ENTRIES_I350 32
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#define E1000_RAR_ENTRIES_82575 16
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#define E1000_RAR_ENTRIES_82576 24
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#define E1000_RAR_ENTRIES_82580 24
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#define E1000_RAR_ENTRIES_I350 32
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#define E1000_SW_SYNCH_MB 0x00000100
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#define E1000_STAT_DEV_RST_SET 0x00100000
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#define E1000_CTRL_DEV_RST 0x20000000
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struct e1000_adv_data_desc {
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__le64 buffer_addr; /* Address of the descriptor's data buffer */
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union {
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u32 data;
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struct {
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u32 datalen :16; /* Data buffer length */
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u32 rsvd :4;
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u32 dtyp :4; /* Descriptor type */
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u32 dcmd :8; /* Descriptor command */
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u32 datalen:16; /* Data buffer length */
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u32 rsvd:4;
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u32 dtyp:4; /* Descriptor type */
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u32 dcmd:8; /* Descriptor command */
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} config;
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} lower;
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union {
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u32 data;
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struct {
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u32 status :4; /* Descriptor status */
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u32 idx :4;
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u32 popts :6; /* Packet Options */
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u32 paylen :18; /* Payload length */
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u32 status:4; /* Descriptor status */
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u32 idx:4;
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u32 popts:6; /* Packet Options */
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u32 paylen:18; /* Payload length */
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} options;
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} upper;
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};
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#define E1000_TXD_DTYP_ADV_C 0x2 /* Advanced Context Descriptor */
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#define E1000_TXD_DTYP_ADV_D 0x3 /* Advanced Data Descriptor */
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#define E1000_ADV_TXD_CMD_DEXT 0x20 /* Descriptor extension (0 = legacy) */
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#define E1000_ADV_TUCMD_IPV4 0x2 /* IP Packet Type: 1=IPv4 */
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#define E1000_ADV_TUCMD_IPV6 0x0 /* IP Packet Type: 0=IPv6 */
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#define E1000_ADV_TUCMD_L4T_UDP 0x0 /* L4 Packet TYPE of UDP */
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#define E1000_ADV_TUCMD_L4T_TCP 0x4 /* L4 Packet TYPE of TCP */
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#define E1000_ADV_TUCMD_MKRREQ 0x10 /* Indicates markers are required */
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#define E1000_ADV_DCMD_EOP 0x1 /* End of Packet */
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#define E1000_ADV_DCMD_IFCS 0x2 /* Insert FCS (Ethernet CRC) */
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#define E1000_ADV_DCMD_RS 0x8 /* Report Status */
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#define E1000_ADV_DCMD_VLE 0x40 /* Add VLAN tag */
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#define E1000_ADV_DCMD_TSE 0x80 /* TCP Seg enable */
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#define E1000_TXD_DTYP_ADV_C 0x2 /* Advanced Context Descriptor */
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#define E1000_TXD_DTYP_ADV_D 0x3 /* Advanced Data Descriptor */
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#define E1000_ADV_TXD_CMD_DEXT 0x20 /* Descriptor extension (0 = legacy) */
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#define E1000_ADV_TUCMD_IPV4 0x2 /* IP Packet Type: 1=IPv4 */
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#define E1000_ADV_TUCMD_IPV6 0x0 /* IP Packet Type: 0=IPv6 */
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#define E1000_ADV_TUCMD_L4T_UDP 0x0 /* L4 Packet TYPE of UDP */
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#define E1000_ADV_TUCMD_L4T_TCP 0x4 /* L4 Packet TYPE of TCP */
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#define E1000_ADV_TUCMD_MKRREQ 0x10 /* Indicates markers are required */
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#define E1000_ADV_DCMD_EOP 0x1 /* End of Packet */
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#define E1000_ADV_DCMD_IFCS 0x2 /* Insert FCS (Ethernet CRC) */
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#define E1000_ADV_DCMD_RS 0x8 /* Report Status */
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#define E1000_ADV_DCMD_VLE 0x40 /* Add VLAN tag */
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#define E1000_ADV_DCMD_TSE 0x80 /* TCP Seg enable */
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/* Extended Device Control */
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#define E1000_CTRL_EXT_NSICR 0x00000001 /* Disable Intr Clear all on read */
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#define E1000_CTRL_EXT_NSICR 0x00000001 /* Disable Intr Clear all on read */
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struct e1000_adv_context_desc {
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union {
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u32 ip_config;
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struct {
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u32 iplen :9;
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u32 maclen :7;
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u32 vlan_tag :16;
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u32 iplen:9;
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u32 maclen:7;
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u32 vlan_tag:16;
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} fields;
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} ip_setup;
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u32 seq_num;
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union {
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u64 l4_config;
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struct {
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u32 mkrloc :9;
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u32 tucmd :11;
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u32 dtyp :4;
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u32 adv :8;
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u32 rsvd :4;
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u32 idx :4;
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u32 l4len :8;
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u32 mss :16;
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u32 mkrloc:9;
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u32 tucmd:11;
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u32 dtyp:4;
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u32 adv:8;
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u32 rsvd:4;
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u32 idx:4;
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u32 l4len:8;
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u32 mss:16;
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} fields;
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} l4_setup;
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};
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/* SRRCTL bit definitions */
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#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
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#define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00
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#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
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#define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000
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#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
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#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
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#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
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#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000
|
||||
#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
|
||||
#define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00
|
||||
#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
|
||||
#define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000
|
||||
#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
|
||||
#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
|
||||
#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
|
||||
#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000
|
||||
#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
|
||||
#define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000
|
||||
#define E1000_SRRCTL_TIMESTAMP 0x40000000
|
||||
#define E1000_SRRCTL_DROP_EN 0x80000000
|
||||
#define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000
|
||||
#define E1000_SRRCTL_TIMESTAMP 0x40000000
|
||||
#define E1000_SRRCTL_DROP_EN 0x80000000
|
||||
|
||||
#define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F
|
||||
#define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00
|
||||
#define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F
|
||||
#define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00
|
||||
|
||||
#define E1000_TX_HEAD_WB_ENABLE 0x1
|
||||
#define E1000_TX_SEQNUM_WB_ENABLE 0x2
|
||||
#define E1000_TX_HEAD_WB_ENABLE 0x1
|
||||
#define E1000_TX_SEQNUM_WB_ENABLE 0x2
|
||||
|
||||
#define E1000_MRQC_ENABLE_RSS_4Q 0x00000002
|
||||
#define E1000_MRQC_ENABLE_VMDQ 0x00000003
|
||||
#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005
|
||||
#define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
|
||||
#define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
|
||||
#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
|
||||
#define E1000_MRQC_ENABLE_RSS_8Q 0x00000002
|
||||
#define E1000_MRQC_ENABLE_RSS_4Q 0x00000002
|
||||
#define E1000_MRQC_ENABLE_VMDQ 0x00000003
|
||||
#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005
|
||||
#define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
|
||||
#define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
|
||||
#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
|
||||
#define E1000_MRQC_ENABLE_RSS_8Q 0x00000002
|
||||
|
||||
#define E1000_VMRCTL_MIRROR_PORT_SHIFT 8
|
||||
#define E1000_VMRCTL_MIRROR_DSTPORT_MASK (7 << E1000_VMRCTL_MIRROR_PORT_SHIFT)
|
||||
#define E1000_VMRCTL_POOL_MIRROR_ENABLE (1 << 0)
|
||||
#define E1000_VMRCTL_UPLINK_MIRROR_ENABLE (1 << 1)
|
||||
#define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE (1 << 2)
|
||||
#define E1000_VMRCTL_MIRROR_PORT_SHIFT 8
|
||||
#define E1000_VMRCTL_MIRROR_DSTPORT_MASK (7 << \
|
||||
E1000_VMRCTL_MIRROR_PORT_SHIFT)
|
||||
#define E1000_VMRCTL_POOL_MIRROR_ENABLE (1 << 0)
|
||||
#define E1000_VMRCTL_UPLINK_MIRROR_ENABLE (1 << 1)
|
||||
#define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE (1 << 2)
|
||||
|
||||
#define E1000_EICR_TX_QUEUE ( \
|
||||
E1000_EICR_TX_QUEUE0 | \
|
||||
E1000_EICR_TX_QUEUE1 | \
|
||||
E1000_EICR_TX_QUEUE2 | \
|
||||
E1000_EICR_TX_QUEUE3)
|
||||
E1000_EICR_TX_QUEUE0 | \
|
||||
E1000_EICR_TX_QUEUE1 | \
|
||||
E1000_EICR_TX_QUEUE2 | \
|
||||
E1000_EICR_TX_QUEUE3)
|
||||
|
||||
#define E1000_EICR_RX_QUEUE ( \
|
||||
E1000_EICR_RX_QUEUE0 | \
|
||||
E1000_EICR_RX_QUEUE1 | \
|
||||
E1000_EICR_RX_QUEUE2 | \
|
||||
E1000_EICR_RX_QUEUE3)
|
||||
E1000_EICR_RX_QUEUE0 | \
|
||||
E1000_EICR_RX_QUEUE1 | \
|
||||
E1000_EICR_RX_QUEUE2 | \
|
||||
E1000_EICR_RX_QUEUE3)
|
||||
|
||||
#define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE
|
||||
#define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE
|
||||
#define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE
|
||||
#define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE
|
||||
|
||||
#define EIMS_ENABLE_MASK ( \
|
||||
E1000_EIMS_RX_QUEUE | \
|
||||
E1000_EIMS_TX_QUEUE | \
|
||||
E1000_EIMS_TCP_TIMER | \
|
||||
E1000_EIMS_OTHER)
|
||||
E1000_EIMS_RX_QUEUE | \
|
||||
E1000_EIMS_TX_QUEUE | \
|
||||
E1000_EIMS_TCP_TIMER | \
|
||||
E1000_EIMS_OTHER)
|
||||
|
||||
/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
|
||||
#define E1000_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */
|
||||
#define E1000_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */
|
||||
#define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
|
||||
#define E1000_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */
|
||||
#define E1000_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */
|
||||
#define E1000_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */
|
||||
#define E1000_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */
|
||||
#define E1000_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */
|
||||
#define E1000_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */
|
||||
#define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */
|
||||
#define E1000_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */
|
||||
#define E1000_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */
|
||||
#define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
|
||||
#define E1000_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */
|
||||
#define E1000_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */
|
||||
#define E1000_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */
|
||||
#define E1000_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */
|
||||
#define E1000_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */
|
||||
#define E1000_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */
|
||||
#define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */
|
||||
|
||||
/* Receive Descriptor - Advanced */
|
||||
union e1000_adv_rx_desc {
|
||||
struct {
|
||||
__le64 pkt_addr; /* Packet buffer address */
|
||||
__le64 hdr_addr; /* Header buffer address */
|
||||
__le64 pkt_addr; /* Packet buffer address */
|
||||
__le64 hdr_addr; /* Header buffer address */
|
||||
} read;
|
||||
struct {
|
||||
struct {
|
||||
|
|
@ -192,79 +193,79 @@ union e1000_adv_rx_desc {
|
|||
__le32 data;
|
||||
struct {
|
||||
__le16 pkt_info; /*RSS type, Pkt type*/
|
||||
__le16 hdr_info; /* Split Header,
|
||||
* header buffer len*/
|
||||
/* Split Header, header buffer len */
|
||||
__le16 hdr_info;
|
||||
} hs_rss;
|
||||
} lo_dword;
|
||||
union {
|
||||
__le32 rss; /* RSS Hash */
|
||||
__le32 rss; /* RSS Hash */
|
||||
struct {
|
||||
__le16 ip_id; /* IP id */
|
||||
__le16 csum; /* Packet Checksum */
|
||||
__le16 ip_id; /* IP id */
|
||||
__le16 csum; /* Packet Checksum */
|
||||
} csum_ip;
|
||||
} hi_dword;
|
||||
} lower;
|
||||
struct {
|
||||
__le32 status_error; /* ext status/error */
|
||||
__le16 length; /* Packet length */
|
||||
__le16 vlan; /* VLAN tag */
|
||||
__le32 status_error; /* ext status/error */
|
||||
__le16 length; /* Packet length */
|
||||
__le16 vlan; /* VLAN tag */
|
||||
} upper;
|
||||
} wb; /* writeback */
|
||||
};
|
||||
|
||||
#define E1000_RXDADV_RSSTYPE_MASK 0x0000000F
|
||||
#define E1000_RXDADV_RSSTYPE_SHIFT 12
|
||||
#define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
|
||||
#define E1000_RXDADV_HDRBUFLEN_SHIFT 5
|
||||
#define E1000_RXDADV_SPLITHEADER_EN 0x00001000
|
||||
#define E1000_RXDADV_SPH 0x8000
|
||||
#define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */
|
||||
#define E1000_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */
|
||||
#define E1000_RXDADV_ERR_HBO 0x00800000
|
||||
#define E1000_RXDADV_RSSTYPE_MASK 0x0000000F
|
||||
#define E1000_RXDADV_RSSTYPE_SHIFT 12
|
||||
#define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
|
||||
#define E1000_RXDADV_HDRBUFLEN_SHIFT 5
|
||||
#define E1000_RXDADV_SPLITHEADER_EN 0x00001000
|
||||
#define E1000_RXDADV_SPH 0x8000
|
||||
#define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */
|
||||
#define E1000_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */
|
||||
#define E1000_RXDADV_ERR_HBO 0x00800000
|
||||
|
||||
/* RSS Hash results */
|
||||
#define E1000_RXDADV_RSSTYPE_NONE 0x00000000
|
||||
#define E1000_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
|
||||
#define E1000_RXDADV_RSSTYPE_IPV4 0x00000002
|
||||
#define E1000_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
|
||||
#define E1000_RXDADV_RSSTYPE_IPV6_EX 0x00000004
|
||||
#define E1000_RXDADV_RSSTYPE_IPV6 0x00000005
|
||||
#define E1000_RXDADV_RSSTYPE_NONE 0x00000000
|
||||
#define E1000_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
|
||||
#define E1000_RXDADV_RSSTYPE_IPV4 0x00000002
|
||||
#define E1000_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
|
||||
#define E1000_RXDADV_RSSTYPE_IPV6_EX 0x00000004
|
||||
#define E1000_RXDADV_RSSTYPE_IPV6 0x00000005
|
||||
#define E1000_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
|
||||
#define E1000_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
|
||||
#define E1000_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
|
||||
#define E1000_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
|
||||
#define E1000_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
|
||||
#define E1000_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
|
||||
|
||||
/* RSS Packet Types as indicated in the receive descriptor */
|
||||
#define E1000_RXDADV_PKTTYPE_NONE 0x00000000
|
||||
#define E1000_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */
|
||||
#define E1000_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPV4 hdr + extensions */
|
||||
#define E1000_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPV6 hdr present */
|
||||
#define E1000_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPV6 hdr + extensions */
|
||||
#define E1000_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
|
||||
#define E1000_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
|
||||
#define E1000_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
|
||||
#define E1000_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
|
||||
#define E1000_RXDADV_PKTTYPE_NONE 0x00000000
|
||||
#define E1000_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */
|
||||
#define E1000_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPV4 hdr + extensions */
|
||||
#define E1000_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPV6 hdr present */
|
||||
#define E1000_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPV6 hdr + extensions */
|
||||
#define E1000_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
|
||||
#define E1000_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
|
||||
#define E1000_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
|
||||
#define E1000_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
|
||||
|
||||
#define E1000_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */
|
||||
#define E1000_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */
|
||||
#define E1000_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */
|
||||
#define E1000_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */
|
||||
#define E1000_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */
|
||||
#define E1000_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
|
||||
#define E1000_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */
|
||||
#define E1000_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */
|
||||
#define E1000_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */
|
||||
#define E1000_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */
|
||||
#define E1000_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */
|
||||
#define E1000_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
|
||||
|
||||
/* LinkSec results */
|
||||
/* Security Processing bit Indication */
|
||||
#define E1000_RXDADV_LNKSEC_STATUS_SECP 0x00020000
|
||||
#define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000
|
||||
#define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000
|
||||
#define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000
|
||||
#define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000
|
||||
#define E1000_RXDADV_LNKSEC_STATUS_SECP 0x00020000
|
||||
#define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000
|
||||
#define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000
|
||||
#define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000
|
||||
#define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000
|
||||
|
||||
#define E1000_RXDADV_IPSEC_STATUS_SECP 0x00020000
|
||||
#define E1000_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000
|
||||
#define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
|
||||
#define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
|
||||
#define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED 0x18000000
|
||||
#define E1000_RXDADV_IPSEC_STATUS_SECP 0x00020000
|
||||
#define E1000_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000
|
||||
#define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
|
||||
#define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
|
||||
#define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED 0x18000000
|
||||
|
||||
/* Transmit Descriptor - Advanced */
|
||||
union e1000_adv_tx_desc {
|
||||
|
|
@ -281,25 +282,26 @@ union e1000_adv_tx_desc {
|
|||
};
|
||||
|
||||
/* Adv Transmit Descriptor Config Masks */
|
||||
#define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
|
||||
#define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
|
||||
#define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
|
||||
#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
|
||||
#define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
|
||||
#define E1000_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
|
||||
#define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
|
||||
#define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
|
||||
#define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
|
||||
#define E1000_ADVTXD_MAC_LINKSEC 0x00040000 /* Apply LinkSec on packet */
|
||||
#define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */
|
||||
#define E1000_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED present in WB */
|
||||
#define E1000_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
|
||||
#define E1000_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */
|
||||
#define E1000_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
|
||||
#define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
|
||||
#define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU*/
|
||||
#define E1000_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */
|
||||
#define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
|
||||
#define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
|
||||
#define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
|
||||
#define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
|
||||
#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
|
||||
#define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
|
||||
#define E1000_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
|
||||
#define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
|
||||
#define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
|
||||
#define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
|
||||
#define E1000_ADVTXD_MAC_LINKSEC 0x00040000 /* Apply LinkSec on pkt */
|
||||
#define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp pkt */
|
||||
#define E1000_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED prsnt in WB */
|
||||
#define E1000_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
|
||||
#define E1000_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */
|
||||
#define E1000_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
|
||||
#define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
|
||||
/* 1st & Last TSO-full iSCSI PDU*/
|
||||
#define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800
|
||||
#define E1000_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */
|
||||
#define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
|
||||
|
||||
/* Context descriptors */
|
||||
struct e1000_adv_tx_context_desc {
|
||||
|
|
@ -309,65 +311,69 @@ struct e1000_adv_tx_context_desc {
|
|||
__le32 mss_l4len_idx;
|
||||
};
|
||||
|
||||
#define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
|
||||
#define E1000_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
|
||||
#define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
|
||||
#define E1000_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
|
||||
#define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
|
||||
#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
|
||||
#define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
|
||||
#define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
|
||||
#define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
|
||||
#define E1000_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
|
||||
#define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
|
||||
#define E1000_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
|
||||
#define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
|
||||
#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
|
||||
#define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
|
||||
#define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
|
||||
/* IPSec Encrypt Enable for ESP */
|
||||
#define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000
|
||||
#define E1000_ADVTXD_TUCMD_MKRREQ 0x00002000 /* Req requires Markers and CRC */
|
||||
#define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
|
||||
#define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
|
||||
#define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000
|
||||
/* Req requires Markers and CRC */
|
||||
#define E1000_ADVTXD_TUCMD_MKRREQ 0x00002000
|
||||
#define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
|
||||
#define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
|
||||
/* Adv ctxt IPSec SA IDX mask */
|
||||
#define E1000_ADVTXD_IPSEC_SA_INDEX_MASK 0x000000FF
|
||||
#define E1000_ADVTXD_IPSEC_SA_INDEX_MASK 0x000000FF
|
||||
/* Adv ctxt IPSec ESP len mask */
|
||||
#define E1000_ADVTXD_IPSEC_ESP_LEN_MASK 0x000000FF
|
||||
#define E1000_ADVTXD_IPSEC_ESP_LEN_MASK 0x000000FF
|
||||
|
||||
/* Additional Transmit Descriptor Control definitions */
|
||||
#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
|
||||
#define E1000_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */
|
||||
#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */
|
||||
#define E1000_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wbk flushing */
|
||||
/* Tx Queue Arbitration Priority 0=low, 1=high */
|
||||
#define E1000_TXDCTL_PRIORITY 0x08000000
|
||||
#define E1000_TXDCTL_PRIORITY 0x08000000
|
||||
|
||||
/* Additional Receive Descriptor Control definitions */
|
||||
#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
|
||||
#define E1000_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. write-back flushing */
|
||||
#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */
|
||||
#define E1000_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. wbk flushing */
|
||||
|
||||
/* Direct Cache Access (DCA) definitions */
|
||||
#define E1000_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
|
||||
#define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
|
||||
#define E1000_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
|
||||
#define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
|
||||
|
||||
#define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
|
||||
#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
|
||||
#define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
|
||||
#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
|
||||
|
||||
#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
|
||||
#define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
|
||||
#define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
|
||||
#define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
|
||||
#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
|
||||
#define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
|
||||
#define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header ena */
|
||||
#define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload ena */
|
||||
#define E1000_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx Desc Relax Order */
|
||||
|
||||
#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
|
||||
#define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
|
||||
#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
|
||||
#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
|
||||
#define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
|
||||
#define E1000_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */
|
||||
#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
|
||||
#define E1000_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */
|
||||
|
||||
#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
|
||||
#define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
|
||||
#define E1000_DCA_TXCTRL_CPUID_SHIFT_82576 24 /* Tx CPUID */
|
||||
#define E1000_DCA_RXCTRL_CPUID_SHIFT_82576 24 /* Rx CPUID */
|
||||
#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
|
||||
#define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
|
||||
#define E1000_DCA_TXCTRL_CPUID_SHIFT_82576 24 /* Tx CPUID */
|
||||
#define E1000_DCA_RXCTRL_CPUID_SHIFT_82576 24 /* Rx CPUID */
|
||||
|
||||
/* Additional interrupt register bit definitions */
|
||||
#define E1000_ICR_LSECPNS 0x00000020 /* PN threshold - server */
|
||||
#define E1000_IMS_LSECPNS E1000_ICR_LSECPNS /* PN threshold - server */
|
||||
#define E1000_ICS_LSECPNS E1000_ICR_LSECPNS /* PN threshold - server */
|
||||
#define E1000_ICR_LSECPNS 0x00000020 /* PN threshold - server */
|
||||
#define E1000_IMS_LSECPNS E1000_ICR_LSECPNS /* PN threshold - server */
|
||||
#define E1000_ICS_LSECPNS E1000_ICR_LSECPNS /* PN threshold - server */
|
||||
|
||||
/* ETQF register bit definitions */
|
||||
#define E1000_ETQF_FILTER_ENABLE (1 << 26)
|
||||
#define E1000_ETQF_IMM_INT (1 << 29)
|
||||
#define E1000_ETQF_1588 (1 << 30)
|
||||
#define E1000_ETQF_QUEUE_ENABLE (1 << 31)
|
||||
#define E1000_ETQF_FILTER_ENABLE (1 << 26)
|
||||
#define E1000_ETQF_IMM_INT (1 << 29)
|
||||
#define E1000_ETQF_1588 (1 << 30)
|
||||
#define E1000_ETQF_QUEUE_ENABLE (1 << 31)
|
||||
/*
|
||||
* ETQF filter list: one static filter per filter consumer. This is
|
||||
* to avoid filter collisions later. Add new filters
|
||||
|
|
@ -376,76 +382,128 @@ struct e1000_adv_tx_context_desc {
|
|||
* Current filters:
|
||||
* EAPOL 802.1x (0x888e): Filter 0
|
||||
*/
|
||||
#define E1000_ETQF_FILTER_EAPOL 0
|
||||
#define E1000_ETQF_FILTER_EAPOL 0
|
||||
|
||||
#define E1000_FTQF_VF_BP 0x00008000
|
||||
#define E1000_FTQF_1588_TIME_STAMP 0x08000000
|
||||
#define E1000_FTQF_MASK 0xF0000000
|
||||
#define E1000_FTQF_MASK_PROTO_BP 0x10000000
|
||||
#define E1000_FTQF_MASK_SOURCE_ADDR_BP 0x20000000
|
||||
#define E1000_FTQF_MASK_DEST_ADDR_BP 0x40000000
|
||||
#define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000
|
||||
#define E1000_FTQF_VF_BP 0x00008000
|
||||
#define E1000_FTQF_1588_TIME_STAMP 0x08000000
|
||||
#define E1000_FTQF_MASK 0xF0000000
|
||||
#define E1000_FTQF_MASK_PROTO_BP 0x10000000
|
||||
#define E1000_FTQF_MASK_SOURCE_ADDR_BP 0x20000000
|
||||
#define E1000_FTQF_MASK_DEST_ADDR_BP 0x40000000
|
||||
#define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000
|
||||
|
||||
#define E1000_NVM_APME_82575 0x0400
|
||||
#define MAX_NUM_VFS 8
|
||||
#define E1000_NVM_APME_82575 0x0400
|
||||
#define MAX_NUM_VFS 7
|
||||
|
||||
#define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof control */
|
||||
#define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof control */
|
||||
#define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */
|
||||
#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
|
||||
#define E1000_DTXSWC_LLE_SHIFT 16
|
||||
#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) /* global VF LB enable */
|
||||
#define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof cntrl */
|
||||
#define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof cntrl */
|
||||
#define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */
|
||||
#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
|
||||
#define E1000_DTXSWC_LLE_SHIFT 16
|
||||
#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) /* global VF LB enable */
|
||||
|
||||
/* Easy defines for setting default pool, would normally be left a zero */
|
||||
#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
|
||||
#define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
|
||||
#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
|
||||
#define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
|
||||
|
||||
/* Other useful VMD_CTL register defines */
|
||||
#define E1000_VT_CTL_IGNORE_MAC (1 << 28)
|
||||
#define E1000_VT_CTL_DISABLE_DEF_POOL (1 << 29)
|
||||
#define E1000_VT_CTL_VM_REPL_EN (1 << 30)
|
||||
#define E1000_VT_CTL_IGNORE_MAC (1 << 28)
|
||||
#define E1000_VT_CTL_DISABLE_DEF_POOL (1 << 29)
|
||||
#define E1000_VT_CTL_VM_REPL_EN (1 << 30)
|
||||
|
||||
/* Per VM Offload register setup */
|
||||
#define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
|
||||
#define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */
|
||||
#define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */
|
||||
#define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */
|
||||
#define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */
|
||||
#define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */
|
||||
#define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */
|
||||
#define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */
|
||||
#define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
|
||||
#define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */
|
||||
#define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
|
||||
#define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */
|
||||
#define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */
|
||||
#define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */
|
||||
#define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */
|
||||
#define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */
|
||||
#define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */
|
||||
#define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */
|
||||
#define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
|
||||
#define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */
|
||||
|
||||
#define E1000_VLVF_ARRAY_SIZE 32
|
||||
#define E1000_VLVF_VLANID_MASK 0x00000FFF
|
||||
#define E1000_VLVF_POOLSEL_SHIFT 12
|
||||
#define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT)
|
||||
#define E1000_VLVF_LVLAN 0x00100000
|
||||
#define E1000_VLVF_VLANID_ENABLE 0x80000000
|
||||
#define E1000_VMOLR_VPE 0x00800000 /* VLAN promiscuous enable */
|
||||
#define E1000_VMOLR_UPE 0x20000000 /* Unicast promisuous enable */
|
||||
#define E1000_DVMOLR_HIDVLAN 0x20000000 /* Vlan hiding enable */
|
||||
#define E1000_DVMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
|
||||
#define E1000_DVMOLR_STRCRC 0x80000000 /* CRC stripping enable */
|
||||
|
||||
#define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
|
||||
#define E1000_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
|
||||
#define E1000_PBRWAC_WALPB 0x00000007 /* Wrap around event on LAN Rx PB */
|
||||
#define E1000_PBRWAC_PBE 0x00000008 /* Rx packet buffer empty */
|
||||
|
||||
#define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
|
||||
#define E1000_VLVF_ARRAY_SIZE 32
|
||||
#define E1000_VLVF_VLANID_MASK 0x00000FFF
|
||||
#define E1000_VLVF_POOLSEL_SHIFT 12
|
||||
#define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT)
|
||||
#define E1000_VLVF_LVLAN 0x00100000
|
||||
#define E1000_VLVF_VLANID_ENABLE 0x80000000
|
||||
|
||||
#define E1000_IOVCTL 0x05BBC
|
||||
#define E1000_IOVCTL_REUSE_VFQ 0x00000001
|
||||
#define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
|
||||
#define E1000_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
|
||||
|
||||
#define E1000_RPLOLR_STRVLAN 0x40000000
|
||||
#define E1000_RPLOLR_STRCRC 0x80000000
|
||||
#define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
|
||||
|
||||
#define E1000_DTXCTL_8023LL 0x0004
|
||||
#define E1000_DTXCTL_VLAN_ADDED 0x0008
|
||||
#define E1000_DTXCTL_OOS_ENABLE 0x0010
|
||||
#define E1000_DTXCTL_MDP_EN 0x0020
|
||||
#define E1000_DTXCTL_SPOOF_INT 0x0040
|
||||
#define E1000_IOVCTL 0x05BBC
|
||||
#define E1000_IOVCTL_REUSE_VFQ 0x00000001
|
||||
|
||||
#define ALL_QUEUES 0xFFFF
|
||||
#define E1000_RPLOLR_STRVLAN 0x40000000
|
||||
#define E1000_RPLOLR_STRCRC 0x80000000
|
||||
|
||||
/* RX packet buffer size defines */
|
||||
#define E1000_RXPBS_SIZE_MASK_82576 0x0000007F
|
||||
#define E1000_TCTL_EXT_COLD 0x000FFC00
|
||||
#define E1000_TCTL_EXT_COLD_SHIFT 10
|
||||
|
||||
#define E1000_DTXCTL_8023LL 0x0004
|
||||
#define E1000_DTXCTL_VLAN_ADDED 0x0008
|
||||
#define E1000_DTXCTL_OOS_ENABLE 0x0010
|
||||
#define E1000_DTXCTL_MDP_EN 0x0020
|
||||
#define E1000_DTXCTL_SPOOF_INT 0x0040
|
||||
|
||||
#define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT (1 << 14)
|
||||
|
||||
#define ALL_QUEUES 0xFFFF
|
||||
|
||||
/* Rx packet buffer size defines */
|
||||
#define E1000_RXPBS_SIZE_MASK_82576 0x0000007F
|
||||
void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable);
|
||||
void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf);
|
||||
void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable);
|
||||
s32 e1000_init_nvm_params_82575(struct e1000_hw *hw);
|
||||
|
||||
u16 e1000_rxpbs_adjust_82580(u32 data);
|
||||
s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data);
|
||||
s32 e1000_set_eee_i350(struct e1000_hw *);
|
||||
s32 e1000_set_eee_i354(struct e1000_hw *);
|
||||
s32 e1000_get_eee_status_i354(struct e1000_hw *, bool *);
|
||||
#define E1000_I2C_THERMAL_SENSOR_ADDR 0xF8
|
||||
#define E1000_EMC_INTERNAL_DATA 0x00
|
||||
#define E1000_EMC_INTERNAL_THERM_LIMIT 0x20
|
||||
#define E1000_EMC_DIODE1_DATA 0x01
|
||||
#define E1000_EMC_DIODE1_THERM_LIMIT 0x19
|
||||
#define E1000_EMC_DIODE2_DATA 0x23
|
||||
#define E1000_EMC_DIODE2_THERM_LIMIT 0x1A
|
||||
#define E1000_EMC_DIODE3_DATA 0x2A
|
||||
#define E1000_EMC_DIODE3_THERM_LIMIT 0x30
|
||||
|
||||
s32 e1000_get_thermal_sensor_data_generic(struct e1000_hw *hw);
|
||||
s32 e1000_init_thermal_sensor_thresh_generic(struct e1000_hw *hw);
|
||||
|
||||
/* I2C SDA and SCL timing parameters for standard mode */
|
||||
#define E1000_I2C_T_HD_STA 4
|
||||
#define E1000_I2C_T_LOW 5
|
||||
#define E1000_I2C_T_HIGH 4
|
||||
#define E1000_I2C_T_SU_STA 5
|
||||
#define E1000_I2C_T_HD_DATA 5
|
||||
#define E1000_I2C_T_SU_DATA 1
|
||||
#define E1000_I2C_T_RISE 1
|
||||
#define E1000_I2C_T_FALL 1
|
||||
#define E1000_I2C_T_SU_STO 4
|
||||
#define E1000_I2C_T_BUF 5
|
||||
|
||||
s32 e1000_set_i2c_bb(struct e1000_hw *hw);
|
||||
s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
|
||||
u8 dev_addr, u8 *data);
|
||||
s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
|
||||
u8 dev_addr, u8 data);
|
||||
void e1000_i2c_bus_clear(struct e1000_hw *hw);
|
||||
#endif /* _E1000_82575_H_ */
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*******************************************************************************
|
||||
|
||||
Intel(R) Gigabit Ethernet Linux driver
|
||||
Copyright(c) 2007-2009 Intel Corporation.
|
||||
Copyright(c) 2007-2013 Intel Corporation.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
|
|
@ -157,7 +157,7 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
|
|||
case E1000_DEV_ID_82576_FIBER:
|
||||
case E1000_DEV_ID_82576_SERDES:
|
||||
case E1000_DEV_ID_82576_QUAD_COPPER:
|
||||
case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
|
||||
case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
|
||||
case E1000_DEV_ID_82576_NS:
|
||||
case E1000_DEV_ID_82576_NS_SERDES:
|
||||
case E1000_DEV_ID_82576_SERDES_QUAD:
|
||||
|
|
@ -168,14 +168,39 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
|
|||
case E1000_DEV_ID_82580_SERDES:
|
||||
case E1000_DEV_ID_82580_SGMII:
|
||||
case E1000_DEV_ID_82580_COPPER_DUAL:
|
||||
case E1000_DEV_ID_82580_QUAD_FIBER:
|
||||
case E1000_DEV_ID_DH89XXCC_SGMII:
|
||||
case E1000_DEV_ID_DH89XXCC_SERDES:
|
||||
case E1000_DEV_ID_DH89XXCC_BACKPLANE:
|
||||
case E1000_DEV_ID_DH89XXCC_SFP:
|
||||
mac->type = e1000_82580;
|
||||
break;
|
||||
case E1000_DEV_ID_I350_COPPER:
|
||||
case E1000_DEV_ID_I350_FIBER:
|
||||
case E1000_DEV_ID_I350_SERDES:
|
||||
case E1000_DEV_ID_I350_SGMII:
|
||||
case E1000_DEV_ID_I350_DA4:
|
||||
mac->type = e1000_i350;
|
||||
break;
|
||||
case E1000_DEV_ID_I210_COPPER_FLASHLESS:
|
||||
case E1000_DEV_ID_I210_SERDES_FLASHLESS:
|
||||
case E1000_DEV_ID_I210_COPPER:
|
||||
case E1000_DEV_ID_I210_COPPER_OEM1:
|
||||
case E1000_DEV_ID_I210_COPPER_IT:
|
||||
case E1000_DEV_ID_I210_FIBER:
|
||||
case E1000_DEV_ID_I210_SERDES:
|
||||
case E1000_DEV_ID_I210_SGMII:
|
||||
mac->type = e1000_i210;
|
||||
break;
|
||||
case E1000_DEV_ID_I211_COPPER:
|
||||
mac->type = e1000_i211;
|
||||
break;
|
||||
|
||||
case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
|
||||
case E1000_DEV_ID_I354_SGMII:
|
||||
case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
|
||||
mac->type = e1000_i354;
|
||||
break;
|
||||
default:
|
||||
/* Should never have loaded on this device */
|
||||
ret_val = -E1000_ERR_MAC_INIT;
|
||||
|
|
@ -189,10 +214,10 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
|
|||
* e1000_setup_init_funcs - Initializes function pointers
|
||||
* @hw: pointer to the HW structure
|
||||
* @init_device: true will initialize the rest of the function pointers
|
||||
* getting the device ready for use. false will only set
|
||||
* MAC type and the function pointers for the other init
|
||||
* functions. Passing false will not generate any hardware
|
||||
* reads or writes.
|
||||
* getting the device ready for use. false will only set
|
||||
* MAC type and the function pointers for the other init
|
||||
* functions. Passing false will not generate any hardware
|
||||
* reads or writes.
|
||||
*
|
||||
* This function must be called by a driver in order to use the rest
|
||||
* of the 'shared' code files. Called by drivers only.
|
||||
|
|
@ -232,8 +257,13 @@ s32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device)
|
|||
case e1000_82576:
|
||||
case e1000_82580:
|
||||
case e1000_i350:
|
||||
case e1000_i354:
|
||||
e1000_init_function_pointers_82575(hw);
|
||||
break;
|
||||
case e1000_i210:
|
||||
case e1000_i211:
|
||||
e1000_init_function_pointers_i210(hw);
|
||||
break;
|
||||
default:
|
||||
DEBUGOUT("Hardware not supported\n");
|
||||
ret_val = -E1000_ERR_CONFIG;
|
||||
|
|
@ -320,11 +350,11 @@ void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
|
|||
* The caller must have a packed mc_addr_list of multicast addresses.
|
||||
**/
|
||||
void e1000_update_mc_addr_list(struct e1000_hw *hw, u8 *mc_addr_list,
|
||||
u32 mc_addr_count)
|
||||
u32 mc_addr_count)
|
||||
{
|
||||
if (hw->mac.ops.update_mc_addr_list)
|
||||
hw->mac.ops.update_mc_addr_list(hw, mc_addr_list,
|
||||
mc_addr_count);
|
||||
mc_addr_count);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -618,20 +648,6 @@ s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
|
|||
return E1000_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_mta_set - Sets multicast table bit
|
||||
* @hw: pointer to the HW structure
|
||||
* @hash_value: Multicast hash value.
|
||||
*
|
||||
* This sets the bit in the multicast table corresponding to the
|
||||
* hash value. This is a function pointer entry point called by drivers.
|
||||
**/
|
||||
void e1000_mta_set(struct e1000_hw *hw, u32 hash_value)
|
||||
{
|
||||
if (hw->mac.ops.mta_set)
|
||||
hw->mac.ops.mta_set(hw, hash_value);
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_hash_mc_addr - Determines address location in multicast table
|
||||
* @hw: pointer to the HW structure
|
||||
|
|
@ -672,14 +688,10 @@ bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
|
|||
* It also does alignment considerations to do the writes in most efficient
|
||||
* way. Also fills up the sum of the buffer in *buffer parameter.
|
||||
**/
|
||||
s32 e1000_mng_host_if_write(struct e1000_hw * hw, u8 *buffer, u16 length,
|
||||
u16 offset, u8 *sum)
|
||||
s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,
|
||||
u16 offset, u8 *sum)
|
||||
{
|
||||
if (hw->mac.ops.mng_host_if_write)
|
||||
return hw->mac.ops.mng_host_if_write(hw, buffer, length,
|
||||
offset, sum);
|
||||
|
||||
return E1000_NOT_IMPLEMENTED;
|
||||
return e1000_mng_host_if_write_generic(hw, buffer, length, offset, sum);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -690,12 +702,9 @@ s32 e1000_mng_host_if_write(struct e1000_hw * hw, u8 *buffer, u16 length,
|
|||
* Writes the command header after does the checksum calculation.
|
||||
**/
|
||||
s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
|
||||
struct e1000_host_mng_command_header *hdr)
|
||||
struct e1000_host_mng_command_header *hdr)
|
||||
{
|
||||
if (hw->mac.ops.mng_write_cmd_header)
|
||||
return hw->mac.ops.mng_write_cmd_header(hw, hdr);
|
||||
|
||||
return E1000_NOT_IMPLEMENTED;
|
||||
return e1000_mng_write_cmd_header_generic(hw, hdr);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -708,27 +717,9 @@ s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
|
|||
* and also checks whether the previous command is completed. It busy waits
|
||||
* in case of previous command is not completed.
|
||||
**/
|
||||
s32 e1000_mng_enable_host_if(struct e1000_hw * hw)
|
||||
s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
|
||||
{
|
||||
if (hw->mac.ops.mng_enable_host_if)
|
||||
return hw->mac.ops.mng_enable_host_if(hw);
|
||||
|
||||
return E1000_NOT_IMPLEMENTED;
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_wait_autoneg - Waits for autonegotiation completion
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Waits for autoneg to complete. Currently no func pointer exists and all
|
||||
* implementations are handled in the generic version of this function.
|
||||
**/
|
||||
s32 e1000_wait_autoneg(struct e1000_hw *hw)
|
||||
{
|
||||
if (hw->mac.ops.wait_autoneg)
|
||||
return hw->mac.ops.wait_autoneg(hw);
|
||||
|
||||
return E1000_SUCCESS;
|
||||
return e1000_mng_enable_host_if_generic(hw);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -961,18 +952,34 @@ s32 e1000_read_mac_addr(struct e1000_hw *hw)
|
|||
}
|
||||
|
||||
/**
|
||||
* e1000_read_pba_num - Read device part number
|
||||
* e1000_read_pba_string - Read device part number string
|
||||
* @hw: pointer to the HW structure
|
||||
* @pba_num: pointer to device part number
|
||||
* @pba_num_size: size of part number buffer
|
||||
*
|
||||
* Reads the product board assembly (PBA) number from the EEPROM and stores
|
||||
* the value in pba_num.
|
||||
* Currently no func pointer exists and all implementations are handled in the
|
||||
* generic version of this function.
|
||||
**/
|
||||
s32 e1000_read_pba_num(struct e1000_hw *hw, u32 *pba_num)
|
||||
s32 e1000_read_pba_string(struct e1000_hw *hw, u8 *pba_num, u32 pba_num_size)
|
||||
{
|
||||
return e1000_read_pba_num_generic(hw, pba_num);
|
||||
return e1000_read_pba_string_generic(hw, pba_num, pba_num_size);
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_read_pba_length - Read device part number string length
|
||||
* @hw: pointer to the HW structure
|
||||
* @pba_num_size: size of part number buffer
|
||||
*
|
||||
* Reads the product board assembly (PBA) number length from the EEPROM and
|
||||
* stores the value in pba_num.
|
||||
* Currently no func pointer exists and all implementations are handled in the
|
||||
* generic version of this function.
|
||||
**/
|
||||
s32 e1000_read_pba_length(struct e1000_hw *hw, u32 *pba_num_size)
|
||||
{
|
||||
return e1000_read_pba_length_generic(hw, pba_num_size);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -1065,7 +1072,7 @@ s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
|
|||
* This is a function pointer entry point called by drivers.
|
||||
**/
|
||||
s32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, u32 offset,
|
||||
u8 data)
|
||||
u8 data)
|
||||
{
|
||||
return e1000_write_8bit_ctrl_reg_generic(hw, reg, offset, data);
|
||||
}
|
||||
|
|
@ -1098,6 +1105,18 @@ void e1000_power_down_phy(struct e1000_hw *hw)
|
|||
hw->phy.ops.power_down(hw);
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_power_up_fiber_serdes_link - Power up serdes link
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Power on the optics and PCS.
|
||||
**/
|
||||
void e1000_power_up_fiber_serdes_link(struct e1000_hw *hw)
|
||||
{
|
||||
if (hw->mac.ops.power_up_serdes)
|
||||
hw->mac.ops.power_up_serdes(hw);
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_shutdown_fiber_serdes_link - Remove link during power down
|
||||
* @hw: pointer to the HW structure
|
||||
|
|
@ -1110,3 +1129,31 @@ void e1000_shutdown_fiber_serdes_link(struct e1000_hw *hw)
|
|||
hw->mac.ops.shutdown_serdes(hw);
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_get_thermal_sensor_data - Gathers thermal sensor data
|
||||
* @hw: pointer to hardware structure
|
||||
*
|
||||
* Updates the temperatures in mac.thermal_sensor_data
|
||||
**/
|
||||
s32 e1000_get_thermal_sensor_data(struct e1000_hw *hw)
|
||||
{
|
||||
if (hw->mac.ops.get_thermal_sensor_data)
|
||||
return hw->mac.ops.get_thermal_sensor_data(hw);
|
||||
|
||||
return E1000_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_init_thermal_sensor_thresh - Sets thermal sensor thresholds
|
||||
* @hw: pointer to hardware structure
|
||||
*
|
||||
* Sets the thermal sensor thresholds according to the NVM map
|
||||
**/
|
||||
s32 e1000_init_thermal_sensor_thresh(struct e1000_hw *hw)
|
||||
{
|
||||
if (hw->mac.ops.init_thermal_sensor_thresh)
|
||||
return hw->mac.ops.init_thermal_sensor_thresh(hw);
|
||||
|
||||
return E1000_SUCCESS;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*******************************************************************************
|
||||
|
||||
Intel(R) Gigabit Ethernet Linux driver
|
||||
Copyright(c) 2007-2009 Intel Corporation.
|
||||
Copyright(c) 2007-2013 Intel Corporation.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
|
|
@ -30,78 +30,81 @@
|
|||
|
||||
#include "e1000_hw.h"
|
||||
|
||||
extern void e1000_init_function_pointers_82575(struct e1000_hw *hw);
|
||||
extern void e1000_rx_fifo_flush_82575(struct e1000_hw *hw);
|
||||
extern void e1000_init_function_pointers_vf(struct e1000_hw *hw);
|
||||
extern void e1000_shutdown_fiber_serdes_link(struct e1000_hw *hw);
|
||||
extern void e1000_init_function_pointers_82575(struct e1000_hw *hw);
|
||||
extern void e1000_rx_fifo_flush_82575(struct e1000_hw *hw);
|
||||
extern void e1000_init_function_pointers_vf(struct e1000_hw *hw);
|
||||
extern void e1000_power_up_fiber_serdes_link(struct e1000_hw *hw);
|
||||
extern void e1000_shutdown_fiber_serdes_link(struct e1000_hw *hw);
|
||||
extern void e1000_init_function_pointers_i210(struct e1000_hw *hw);
|
||||
|
||||
s32 e1000_set_mac_type(struct e1000_hw *hw);
|
||||
s32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device);
|
||||
s32 e1000_init_mac_params(struct e1000_hw *hw);
|
||||
s32 e1000_init_nvm_params(struct e1000_hw *hw);
|
||||
s32 e1000_init_phy_params(struct e1000_hw *hw);
|
||||
s32 e1000_init_mbx_params(struct e1000_hw *hw);
|
||||
s32 e1000_get_bus_info(struct e1000_hw *hw);
|
||||
s32 e1000_set_obff_timer(struct e1000_hw *hw, u32 itr);
|
||||
s32 e1000_set_mac_type(struct e1000_hw *hw);
|
||||
s32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device);
|
||||
s32 e1000_init_mac_params(struct e1000_hw *hw);
|
||||
s32 e1000_init_nvm_params(struct e1000_hw *hw);
|
||||
s32 e1000_init_phy_params(struct e1000_hw *hw);
|
||||
s32 e1000_init_mbx_params(struct e1000_hw *hw);
|
||||
s32 e1000_get_bus_info(struct e1000_hw *hw);
|
||||
void e1000_clear_vfta(struct e1000_hw *hw);
|
||||
void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value);
|
||||
s32 e1000_force_mac_fc(struct e1000_hw *hw);
|
||||
s32 e1000_check_for_link(struct e1000_hw *hw);
|
||||
s32 e1000_reset_hw(struct e1000_hw *hw);
|
||||
s32 e1000_init_hw(struct e1000_hw *hw);
|
||||
s32 e1000_setup_link(struct e1000_hw *hw);
|
||||
s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed,
|
||||
u16 *duplex);
|
||||
s32 e1000_disable_pcie_master(struct e1000_hw *hw);
|
||||
s32 e1000_force_mac_fc(struct e1000_hw *hw);
|
||||
s32 e1000_check_for_link(struct e1000_hw *hw);
|
||||
s32 e1000_reset_hw(struct e1000_hw *hw);
|
||||
s32 e1000_init_hw(struct e1000_hw *hw);
|
||||
s32 e1000_setup_link(struct e1000_hw *hw);
|
||||
s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex);
|
||||
s32 e1000_disable_pcie_master(struct e1000_hw *hw);
|
||||
void e1000_config_collision_dist(struct e1000_hw *hw);
|
||||
void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
|
||||
void e1000_mta_set(struct e1000_hw *hw, u32 hash_value);
|
||||
u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr);
|
||||
void e1000_update_mc_addr_list(struct e1000_hw *hw,
|
||||
u8 *mc_addr_list, u32 mc_addr_count);
|
||||
s32 e1000_setup_led(struct e1000_hw *hw);
|
||||
s32 e1000_cleanup_led(struct e1000_hw *hw);
|
||||
s32 e1000_check_reset_block(struct e1000_hw *hw);
|
||||
s32 e1000_blink_led(struct e1000_hw *hw);
|
||||
s32 e1000_led_on(struct e1000_hw *hw);
|
||||
s32 e1000_led_off(struct e1000_hw *hw);
|
||||
u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr);
|
||||
void e1000_update_mc_addr_list(struct e1000_hw *hw, u8 *mc_addr_list,
|
||||
u32 mc_addr_count);
|
||||
s32 e1000_setup_led(struct e1000_hw *hw);
|
||||
s32 e1000_cleanup_led(struct e1000_hw *hw);
|
||||
s32 e1000_check_reset_block(struct e1000_hw *hw);
|
||||
s32 e1000_blink_led(struct e1000_hw *hw);
|
||||
s32 e1000_led_on(struct e1000_hw *hw);
|
||||
s32 e1000_led_off(struct e1000_hw *hw);
|
||||
s32 e1000_id_led_init(struct e1000_hw *hw);
|
||||
void e1000_reset_adaptive(struct e1000_hw *hw);
|
||||
void e1000_update_adaptive(struct e1000_hw *hw);
|
||||
s32 e1000_get_cable_length(struct e1000_hw *hw);
|
||||
s32 e1000_validate_mdi_setting(struct e1000_hw *hw);
|
||||
s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
s32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg,
|
||||
u32 offset, u8 data);
|
||||
s32 e1000_get_phy_info(struct e1000_hw *hw);
|
||||
s32 e1000_get_cable_length(struct e1000_hw *hw);
|
||||
s32 e1000_validate_mdi_setting(struct e1000_hw *hw);
|
||||
s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
s32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, u32 offset,
|
||||
u8 data);
|
||||
s32 e1000_get_phy_info(struct e1000_hw *hw);
|
||||